Design Verification- Manager Engineering

Design Verification- Manager Engineering

Job Description

Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering the first pass success of complex IPs using the latest advanced verification languages and methodology. The person would be working with experienced and motivated team of Designers and Verification resource and able to address the verification challenges in the context of the IP, Subsystem, and overall system, using simulation and formal verification and actively participate in supporting the debug at IP or SoC Level. Technical Skillset Required: IP verification Using SV/UVM SOC Verification using C/SV VIP Integration Interconnect Protocols:





AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (3 ) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI Memory Interfaces: DDR or HBM I/O Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incisive Technical Documentation: Testbench Specification, Test Plan Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

▶️ Design Verification- Manager Engineering
🖊️ Tessolve Semiconductor
📍 Secunderabad