Senior Verification Engineer

Senior Verification Engineer

04 Jan
|
Koch Industries
|
Bengaluru

04 Jan

Koch Industries

Bengaluru

Sr Verification IC EngineerThe Role:



The Verification Engineer will define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals. He/She will also be responsible for the mixed-signal simulations of the SOC



The key responsibilities of a Verification engineer comprise:



- Define overall verification strategies, methodologies, and simulation environment

- Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.

- Develop,





maintain and publish verification specifications.

- Analyze and debug simulation failures

- Generates code coverage and functional coverage report

- Run gate level simulation and debug them.

- Perform the constraint assertion-based verification



Required Qualifications and Skills:

- BS in EE with 3+ years of experience or MS in EE with 1+ year experience

- Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti

- Fluent in verification language such asUVM/OVM/System Verilog, Vera, Verilog

- Experience in writing Test-plans and creating directed and random test cases

- Strong scripting skills inPerl, Python, Linux shells etc.

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